1. Field of the Disclosure
The disclosure relates generally to an apparatus and method for ion implantation, and more particularly to an apparatus and method for partial ion implantation.
2. Brief Description of Related Technology
Many unit processes are formed to fabricate a semiconductor memory, such as a dynamic random access memory (DRAM). These unit processes include a stacking process, an etching process, an ion implantation process, a photolithography process, etc., and are generally carried out in wafers. Ion implantation is a process in which dopant ions, such as boron or arsenic, are accelerated by a high electric field, and passed through the surface of a wafer. The electrical characteristics of a material can be changed by an ion implantation process.
Ion implantation into a wafer is usually performed at the same dose throughout the entire domain of the wafer. While this may be preferable in the ion implantation process, it also may adversely affect other unit processes. As a result of certain unit processes, the thicknesses or the etching degrees of stacked films are not uniform throughout the entire domain of the wafer because many parameters of the respective unit processes cannot be precisely controlled. Accordingly, there are unexpected tolerances or tolerances due to the parameters, which are not precisely controlled. For example, in the fabrication of a transistor, a junction region usually is formed having a lightly doped drain (LDD) structure for suppressing a short route effect. For this reason, a spacer film is formed on the side wall of a gate, and deep source/drain regions are formed by ion implantation using the spacer film and the gate as an ion implantation mask. However, during unit processes (a stacking process, a mask process, and an etching process) performed to form the spacer film, the length or thickness of the spacer film cannot be substantially uniform throughout the entire domain of the wafer. Further, ion implantation cannot be uniformly performed throughout the entire domain of the wafer. That is, there is a deviation of dopant doses between the center and the edge of the wafer. Due to this non-uniformity, many parameters including the threshold voltage of the transistor are different in the same wafer. This may cause serious problems in consideration of the present trend of the wafer towards the increase in size.